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NUP2114UPXV5 Transient Voltage Suppressors
Low Capacitance ESD Protection for High Speed Data
The NUP2114UPXV5 transient voltage suppressor is designed to protect high speed data lines from ESD. Ultra-low capacitance and high level of ESD protection makes this device well suited for use in USB 2.0 applications.
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I/O VP
* * * * * * * * * * * * *
Low Capacitance 0.8 pF Stand Off Voltage: 5 V Low Leakage Protection for the Following IEC Standards: IEC 61000-4-2 Level 4 ESD Protection UL Flammability Rating of 94 V-0 This is a Pb-Free Device High Speed Communication Line Protection USB 2.0 High Speed Data Line and Power Line Protection Monitors and Flat Panel Displays MP3 Gigabit Ethernet Notebook Computers Digital Video Interface (DVI) and HDMI
I/O
5 1 SOT-553 CASE 463B
MARKING DIAGRAM
P2MG G
Typical Applications
1
P2 = Specific Device Code M = Date Code G = Pb-Free Package (Note: Microdot may be in either location)
PIN CONNECTIONS
VP 1 5 I/O
MAXIMUM RATINGS (TJ = 25C unless otherwise noted)
Rating Operating Junction Temperature Range Storage Temperature Range Lead Solder Temperature - Maximum (10 Seconds) Human Body Model (HBM) Machine Model (MM) IEC 61000-4-2 Contact (ESD) Symbol TJ Tstg TL ESD Value -40 to +125 -55 to +150 260 16000 400 13000 Unit C C C NC V 3 4 I/O VN 2
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
ORDERING INFORMATION
Device Package Shipping
See Application Note AND8308/D for further description of survivability specs.
NUP2114UPXV5T1G SOT-553 4000/Tape & Reel (Pb-Free) For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2009
September, 2009 - Rev. 1
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Publication Order Number: NUP2114UPXV5/D
NUP2114UPXV5
ELECTRICAL CHARACTERISTICS
(TA = 25C unless otherwise noted) Symbol IPP VC VRWM IR VBR IT IF VF Ppk C Parameter Maximum Reverse Peak Pulse Current Clamping Voltage @ IPP Working Peak Reverse Voltage Maximum Reverse Leakage Current @ VRWM Breakdown Voltage @ IT Test Current Forward Current Forward Voltage @ IF Peak Power Dissipation Max. Capacitance @ VR = 0 and f = 1.0 MHz IPP VC VBR VRWM IR VF IT V IF I
Uni-Directional TVS
*See Application Note AND8308/D for detailed explanations of datasheet parameters.
ELECTRICAL CHARACTERISTICS (TJ=25C unless otherwise specified)
Parameter Reverse Working Voltage Breakdown Voltage Reverse Leakage Current Junction Capacitance Junction Capacitance Clamping Voltage Clamping Voltage Symbol VRWM VBR IR CJ CJ VC VC (Note 1) IT = 1 mA, (Note 2) VRWM = 5 V VR = 0 V, f = 1 MHz between I/O Pins and GND VR = 0 V, f = 1 MHz between I/O Pins @ IPP = 1 A (Note 3) Per IEC 61000-4-2 (Note 4) Figures 1 and 2 0.8 0.4 6.0 1.0 1.0 0.5 9.1 Conditions Min Typ Max 5.0 Unit V V mA pF pF V V
1. TVS devices are normally selected according to the working peak reverse voltage (VRWM), which should be equal or greater than the DC or continuous peak operating voltage level. 2. VBR is measured at pulse test current IT. 3. Surge current waveform per Figure 5. 4. Typical waveform. For test procedure see Figures 3 and 4 and Application Note AND8307/D.
Figure 1. ESD Clamping Voltage Screenshot Positive 8 kV Contact per IEC61000-4-2
Figure 2. ESD Clamping Voltage Screenshot Negative 8 kV Contact per IEC61000-4-2
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NUP2114UPXV5
IEC 61000-4-2 Spec.
Test Voltage (kV) 2 4 6 8 First Peak Current (A) 7.5 15 22.5 30 Current at 30 ns (A) 4 8 12 16 Current at 60 ns (A) 2 4 6 8 I @ 60 ns 10% tP = 0.7 ns to 1 ns I @ 30 ns IEC61000-4-2 Waveform Ipeak 100% 90%
Level 1 2 3 4
Figure 3. IEC61000-4-2 Spec
ESD Gun
TVS
Oscilloscope
50 W Cable
50 W
Figure 4. Diagram of ESD Test Setup The following is taken from Application Note AND8308/D - Interpretation of Datasheet Parameters for ESD Devices. ESD Voltage Clamping
For sensitive circuit elements it is important to limit the voltage that an IC will be exposed to during an ESD event to as low a voltage as possible. The ESD clamping voltage is the voltage drop across the ESD protection diode during an ESD event per the IEC61000-4-2 waveform. Since the IEC61000-4-2 was written as a pass/fail spec for larger
100 % OF PEAK PULSE CURRENT 90 80 70 60 50 40 30 20 10 0 0 20 tP tr
systems such as cell phones or laptop computers it is not clearly defined in the spec how to specify a clamping voltage at the device level. ON Semiconductor has developed a way to examine the entire voltage waveform across the ESD protection diode over the time domain of an ESD pulse in the form of an oscilloscope screenshot, which can be found on the datasheets for all ESD protection diodes. For more information on how ON Semiconductor creates these screenshots and how to interpret them please refer to AND8307/D.
PEAK VALUE IRSM @ 8 ms PULSE WIDTH (tP) IS DEFINED AS THAT POINT WHERE THE PEAK CURRENT DECAY = 8 ms HALF VALUE IRSM/2 @ 20 ms
40 t, TIME (ms)
60
80
Figure 5. 8 X 20 ms Pulse Waveform
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NUP2114UPXV5
PACKAGE DIMENSIONS
SOT-553, 6 LEAD CASE 463B-01 ISSUE B
D -X-
5 4 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETERS 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD FINISH THICKNESS. MINIMUM LEAD THICKNESS IS THE MINIMUM THICKNESS OF BASE MATERIAL. DIM A b c D E e L HE MILLIMETERS NOM MAX 0.55 0.60 0.22 0.27 0.13 0.18 1.60 1.70 1.20 1.30 0.50 BSC 0.10 0.20 0.30 1.50 1.60 1.70 MIN 0.50 0.17 0.08 1.50 1.10 INCHES NOM 0.022 0.009 0.005 0.063 0.047 0.020 BSC 0.004 0.008 0.059 0.063 MIN 0.020 0.007 0.003 0.059 0.043 MAX 0.024 0.011 0.007 0.067 0.051 0.012 0.067
A
L
1
2
3
E -Y- b
HE
e
5 PL M
c XY
0.08 (0.003)
SOLDERING FOOTPRINT*
0.3 0.0118 0.45 0.0177 1.35 0.0531 1.0 0.0394
0.5 0.5 0.0197 0.0197
SCALE 20:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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NUP2114UPXV5/D

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